1. Field of the Invention
The present invention relates to an analog-to-digital conversion circuit having a multi-stage pipeline (multi-step flash) structure.
2. Description of the Background Art
In recent years, the demands for analog-to-digital conversion circuits (A/D converters) for processing video signals have increased with the progress of digital processing techniques for video signals. High-speed conversion operations are required for analog-to-digital conversion circuits for processing video signals. Conventionally, therefore, two-step flash (two-step parallel) systems have been widely used.
As the number of converted bits increases, however, sufficient conversion accuracy has not been obtained in the two-step flash systems. Therefore, analog-to-digital conversion circuits having multi-stage pipeline (step-flash) structures have been developed.
FIG. 38 is a block diagram showing the structure of a conventional analog-to-digital conversion circuit having a multi-stage pipeline structure. The analog-to-digital conversion circuit shown in FIG. 38 has a 10-bit four-stage pipeline structure. The analog-to-digital conversion circuit is disclosed in JP-A-9-69777, for example.
In FIG. 38, the analog-to-digital conversion circuit 101 comprises a sample-and-hold circuit 102, a first-stage circuit 103, a second-stage circuit 104, a third-stage circuit 105, a fourth-stage circuit 106, a plurality of latch circuits 107, and an output circuit 108.
Each of the first (initial)- to third-stage circuits 103 to 105 comprises a sub-A/D (Analog-to-Digital) converter 109, a D/A (Digital-to-Analog) converter 110, and a subtraction amplification circuit (a differential amplifier) 111. The fourth (final)-stage circuit 106 comprises only a sub-A/D converter 109.
The first-stage circuit 103 has a 4-bit configuration, and each of the second- to fourth-stage circuits 104 to 106 has a 2-bit configuration. In each of the first- to third-stage circuits 103 to 105, the respective numbers of bits (bit configurations) of the sub-A/D converter 109 and the D/A converter 110 are set to the same value.
The operations of the analog-to-digital conversion circuit 101 will be then described. The sample-and-hold circuit 102 samples an analog input signal Vin, and holds the sampled analog input signal for a predetermined time period. The analog input signal Vin outputted from the sample-and-hold circuit 102 is transferred to the first-stage circuit 103.
In the first-stage circuit 103, the sub-A/D converter 109 subjects the analog input signal Vin to A/D (analog-to-digital) conversion. A digital output (29, 28, 27, 26), which is the result of the A/D conversion by the sub-A/D converter 109, is transferred to the D/A converter 110, and is also transferred to the output circuit 108 through the four latch circuits 107. The subtraction amplification circuit 111 amplifies the difference between the result of D/A (digital-to-analog) conversion by the D/A converter 110 and the analog input signal Vin. An output from the subtraction amplification circuit 111 is transferred to the second-stage circuit 104.
The second-stage circuit 104 performs the same operations as those of the first-stage circuit 103 with respect to the output from the subtraction amplification circuit 111 in the first-stage circuit 103. Further, the third-stage circuit 105 performs the same operations as those of the first-stage circuit 103 with respect to an output from the subtraction amplification circuit 111 in the second-stage circuit 104. An intermediate high order 2-bit digital output (25, 24) is obtained from the second-stage circuit 104, and an intermediate low order 2-bit digital output (23, 22) is obtained from the third-stage circuit 105.
In the fourth-stage circuit 106, the sub-A/D converter 109 subjects the output from the subtraction amplification circuit 111 in the third-stage circuit 105 to A/D conversion, thereby obtaining a low order 2-bit digital output (21, 20).
The digital outputs from the first- to fourth-stage circuits 103 to 106 simultaneously reach the output circuit 108 through the respective latch circuits 107. That is, the latch circuits 107 are provided to synchronize the respective digital outputs from the circuits 103 to 106 with each other.
The output circuit 108 outputs a 10-bit digital output Dout of the analog input signal Vin in parallel after digital correction processing, when required.
In each of the first- to third-stage circuits 103 to 105 in the analog-to-digital conversion circuit 101, the subtraction amplification circuit 111 amplifies the difference between the analog input signal Vin or the output from the subtraction amplification circuit 111 in the preceding stage of circuit 103 or 104 and the result of the D/A conversion of the digital output thereof.
Even if the number of converted bits increases to reduce the LSB (Least Significant Bit), therefore, the resolution of each of comparators constituting the sub-A/D converter 109 can be substantially improved, thereby obtaining sufficient conversion accuracy.
FIG. 39 is a circuit diagram of the sub-A/D converter 109 and the D/A converter 110 in the analog-to-digital conversion circuit 101 shown in FIG. 38. The sub A/D converter 109 shown in FIG. 39 is a total parallel comparison (flash) system sub-A/D converter, and the D/A converter 110 is a capacitance array system D/A converter.
The sub-A/D converter 109 comprises n resistors R and n comparators D1 to Dn. All the resistors R have the same resistance value, and are connected in series between a node N31 receiving a high-potential side reference voltage VRT and a node N32 receiving a low-potential side reference voltage VRB. Let VR (1) to VR (n) respectively be potentials at nodes N41 to N4n among the n resistors R between the node N32 and the node N31.
An input signal VI (the analog input signal Vin or the output from the subtraction amplification circuit 111 in the preceding stage of circuit 103, 104, or 105) is inputted to positive input terminals of the comparators D1 to Dn. Further, the potentials VR (1) to VR (n) at the nodes N41 to N4n are respectively applied to negative input terminals of the comparators D1 to Dn.
Consequently, outputs from the comparators D1 to Dn enter a high level, respectively, when the input signal VI is higher than the potentials VR (1) to VR (n), while entering a low level, respectively, when the input signal VI is lower than the potentials VR (1) to VR (n).
The D/A converter 110 comprises respective n switches E1 to En, F1 to Fn, G1 to Gn, and H1 to Hn, n positive-side capacitors B1 to Bn, and n negative-side capacitors C1 to Cn which are respectively connected to one another in an array shape.
All the capacitors B1 to Bn and the capacitors C1 to Cn have the same capacitance value c. A differential positive side output voltage VDA (+) is generated from one terminal (hereinafter referred to as an output terminal) of each of the capacitors B1 to Bn, and a differential negative side output voltage VDA (xe2x88x92) is generated from one terminal (hereinafter referred to as an output terminal) of each of the capacitors C1 to Cn. The other terminal of each of the capacitors B1 to Bn and C1 to Cn is referred to as an input terminal.
Respective one terminals of the switches E1 to En are connected to the node N31, and the other terminals thereof are respectively connected to the input terminals of the capacitors B1 to Bn. Respective one terminals of the switches F1 to Fn are connected to the node N31, and the other terminals thereof are respectively connected to the input terminals of the capacitors C1 to Cn. Respective one terminals of the switches G1 to Gn are connected to the node N32, and the other terminals thereof are respectively connected to the input terminals of the capacitors B1 to Bn. Respective one terminals of the switches H1 to Hn are connected to the node N32, and the other terminals thereof are respectively connected to the input terminals of the capacitors C1 to Cn.
The switches E1 to En, F1 to Fn, G1 to Gn, H1 to Hn constitute four series of switches. For example, the switches E1, F1, G1, and H1 constitute one series of switches, and the switches En, Fn, Gn, and Hn constitute one series of switches. The switches E1 to En, F1 to Fn, G1 to Gn, and H1 to Hn respectively perform on-off operations in accordance with the output levels of the comparators D1 to Dn. For example, when the output from the comparator Dn is at a high level, the switches En and Hn are turned on, and the switches Gn and Fn are turned off. Conversely, when the output from the comparator Dn is at a low level, the switches En and Hn are turned off, and the switches Gn and Fn are turned on.
The operations of the D/A converter 110 will be then described. In the initial conditions, both potentials at the input and output terminals of each of the capacitors B1 to Bn are 0 volt. All the switches E1 to En, F1 to Fn, G1 to Gn, and H1 to Hn are turned off. Consequently, in the initial conditions, the quantity of charges (electricity) Q1 stored in all the capacitors B1 to Bn and C1 to Cn is zero.
When the outputs from m of the n comparators D1 to Dn enter a high level, m of the n switches E1 to En are turned on and the (nxe2x88x92m) switches are turned off, and (nxe2x88x92m) of the switches G1 to Gn are turned on and the m switches are turned off. Charges Q2 stored in all the capacitors B1 to Bn are expressed by the following equation (A1) in accordance with the on-off operations of the switches E1 to En or the switches G1 to Gn:
Q2=m(VRTxe2x88x92VDA(+))c+(nxe2x88x92m)(VRBxe2x88x92VDA(+)) cxe2x80x83xe2x80x83(A1) 
From the principle of conservation of charge, Q1=Q2. Consequently, the differential positive side output voltage VDA (+) is expressed by the following equation (A2):
VDA(+)=VRB+m(VRTxe2x88x92VRB)/nxe2x80x83xe2x80x83(A2) 
On the other hand, when the outputs from m of the n comparators D1 to Dn enter a high level, m of the n switches H1 to Hn are turned on and the (nxe2x88x92m) switches are turned off, and (nxe2x88x92m) of the switches F1 to Fn are turned on and the m switches are turned off. Charges Q3 stored in all the capacitors C1 to Cn are expressed by the following equation (A3) in accordance with the on-off operations of the switches H1 to Hn or the switches F1 to Fn:
Q3=(nxe2x88x92m)(VRTxe2x88x92VDA(xe2x88x92))c+m(VRBxe2x88x92VDA(xe2x88x92))cxe2x80x83xe2x80x83(A3) 
From the principle of conservation of charge, Q1=Q3. Consequently, the differential negative side output voltage VDA (xe2x88x92) is expressed by the foregoing equations (A4):
VDA(xe2x88x92)=VRTxe2x88x92m(VRTxe2x88x92VRB)/nxe2x80x83xe2x80x83(A4) 
Consequently, a difference voltage xcex94VDA is expressed by the following equation (A5):
xcex94VDA=VDA(+)xe2x88x92VDA(xe2x88x92)=VRBxe2x88x92VRT+2m(VRTxe2x88x92VRB)/nxe2x80x83xe2x80x83(A5) 
FIG. 40 is a circuit diagram showing the principle of the operations of the subtraction amplification circuit 111 in the analog-to-digital conversion circuit 101 shown in FIG. 38. FIG. 41 is a diagram for explaining the operations of the subtraction amplification circuit 111 shown in FIG. 40. The subtraction amplification circuit 111 shown in FIG. 40 is a subtraction amplification circuit using a complete differential system. The structure of the subtraction amplification circuit 111 is disclosed in JP-A-11-88173.
In the subtraction amplification circuit 111 shown in FIG. 40, an inverse input terminal of an operational amplifier 100 is connected to a node Na, and a non-inverse input terminal thereof is connected to a node Nb. Further, an inverse output terminal of the operational amplifier 100 is connected to a node NO1, and is connected to the inverse input terminal through a capacitor 20a. A non-inverse output terminal thereof is connected to a node N02, and is connected to the non-inverse input terminal through a capacitor 20b. 
The node Na is grounded through a switch SW11, and the node Nb is grounded through a switch SW12. Further, the node Na is connected to a node N11 through a capacitor 30a, and is connected to a node N12 through a capacitor 40a. The node Nb is connected to a node N21 through a capacitor 30b, and is connected to a node N22 through a capacitor 40b. A switch SW13 is connected between the nodes NO1 and NO2. The switch SW13 operates at the same timing as the switches SW11 and SW12.
The analog input signal Vin or the output from each of the subtraction amplification circuits 111 in the preceding stage of circuit 103, 104, or 105 is fed as a differential voltage xcex94V1 to the subtraction amplification circuit 111. xcex94Vi=Vi(+)xe2x88x92Vi(xe2x88x92). Further, the result of the D/A conversion by the D/A converter 110 in the same stage is fed as a differential voltage xcex94VDA to the subtraction amplification circuit 111. xcex94VDA=VDA(+)xe2x88x92DVA(xe2x88x92).
A voltage which changes from Vi(+) to VA1 is inputted to the node Nil, a voltage which changes from VA2 to VDA (+) is inputted to the node N12, a voltage which changes from Vi (xe2x88x92) to VA1 is inputted to the node N21, and a voltage which changes from VA2 to VDA (xe2x88x92) is inputted to the node N22.
Referring now to FIG. 41, the operations of the subtraction amplification circuit 111 shown in FIG. 40 will be described. Let C be the capacitance value of each of the capacitors 20a and 20b, and let KC be the capacitance value of each of the capacitors 30a, 30b, 40a, and 40b. K is a constant. Further, let VG be a ground potential.
The switches SW11 and SW12 are first turned on. At this time, the switch SW13 is also turned on. The voltage Vi (+) is inputted to the node N11, the set voltage VA2 is inputted to the node N12, the voltage Vi (xe2x88x92) is inputted to the node N21, and the set voltage VA2 is inputted to the node N22. Consequently, potentials at the nodes NO1 and NO2 are ground potentials VG.
The switches SW11 and SW12 are then turned off. At this time, the switch SW13 is also turned off. The set voltage VA1 is inputted to the node N11, the voltage VDA (+) is inputted to the node N12, the set voltage VA1 is inputted to the node N21, and the voltage VDA (xe2x88x92) is inputted to the node N22. Consequently, voltages at the nodes NO1 and NO2 are respectively VO (+) and VO (xe2x88x92).
When the voltages VO (+) and VO (xe2x88x92) at the nodes NO1 and NO2 are found from the principle of conservation of charge, the following equation is obtained:
VO(+)=VG+{V1(+)xe2x88x92VDA(+)}K+(VA1xe2x88x92VA2)K 
VO(xe2x88x92)=VG+{V1(xe2x88x92)xe2x88x92VDA(xe2x88x92)}K+(VA1xe2x88x92VA2)K 
Consequently, a differential voltage xcex94VO is expressed by the following equation:
xcex94VO=VO(+)=VO(xe2x88x92)={Vi(+)xe2x88x92Vi(xe2x88x92)}Kxe2x88x92{VDA(+)xe2x88x92VDA(xe2x88x92)}K={xcex94Vixe2x88x92xcex94VDA}K 
In such a way, the subtraction amplification circuit 111 shown in FIG. 40 performs subtraction of a difference voltage xcex94Vi supplied from the preceding stage of circuit and the differential voltage xcex94VDA supplied from the D/A converter 110 in the same stage and amplification of the result of the subtraction.
In this case, the set voltages VA1 and VA2 can be arbitrarily set. Consequently, a voltage at the time of equalizing outputs from the sample-and-hold circuit 102 or outputs from the subtraction amplification circuit 111 in the preceding stage can be used as the set voltage VA1. Further, an external voltage can be used as the set voltage VA2.
In such a way, the voltages Vi (+) and Vi (xe2x88x92) which are analog input signals can be respectively inputted to the nodes N11 and N21 without passing through switches. Accordingly, noise is reduced, and a low-voltage operation can be performed. Consequently, it is possible to reduce the voltage of the analog-to-digital conversion circuit 101 and increase the accuracy thereof.
FIG. 42 is a circuit diagram showing the specific structures of the D/A converter 110 and the subtraction amplification circuit 111 shown in FIG. 40 in a case where the subtraction amplification circuit 111 is used in the analog-to-digital conversion circuit 101 shown in FIG. 38. The structures of the D/A converter 110 and the subtraction amplification circuit 111 are disclosed in JP-A-11-88173, for example.
In FIG. 42, a node N30 in the D/A converter 110 is connected to the input terminals of the capacitors B1 to Bn, respectively, through switches S1 to Sn. Further, the node N30 is connected to the input terminals of the capacitors C1 to Cn, respectively, through switches T1 to Tn. The set voltage VA2 is inputted to the node N30, the high-potential side reference voltage VRT is inputted to the node N31, and the low-potential side reference voltage VRB is inputted to the node N32. The output terminals of the capacitors B1 to Bn are connected to the node Na in the subtraction amplification circuit 111, and the output terminals of the capacitors C1 to Cn are connected to the node Nb in the subtraction amplification circuit 111.
The node Na in the subtraction amplification circuit 111 is connected to the node N11 through the capacitor 30a, and the node Nb is connected to the node N21 through the capacitor 30b. The voltage Vi (+) is inputted to the node N11, and the voltage Vi (xe2x88x92) is inputted to the node N21.
The capacitance values of the capacitors 20a and 20b are respectively C, and the capacitance values of the capacitors 30a and 30b are respectively KC. Further, the capacitance values of the capacitors B1 to Bn and C1 to Cn are respectively KC/n. K is a constant.
The operations of the D/A converter 110 and the subtraction amplification circuit 111 shown in FIG. 42 will be then described.
The switches SW11 and SW12 are first turned on. At this time, the switch SW13 is also turned on. The switches S1 to Sn and T1 to Tn are turned on. Consequently, a set voltage VA2 is inputted to the input terminals of the capacitors B1 to Bn and C1 to Cn. Further, the voltage Vi (+) is inputted to the node N11, and the voltage Vi (xe2x88x92) is inputted to the node N21. Consequently, potentials at the nodes NO1 and NO2 are ground potentials.
The switches SW11 and SW12 are then turned off. At this time, the switch SW13 is also turned off. The switches S1 to Sn and T1 to Tn are turned off. The switches E1 to En, F1 to Fn, G1 to Gn, and H1 to Hn are respectively turned on or off in accordance with the output levels of the comparators D1 to Dn shown in FIG. 38, and voltages are respectively applied to the input terminals of the capacitors B1 to Bn and C1 to Cn.
At this time, both the voltages Vi (+) and Vi (xe2x88x92) inputted to the nodes N11 and N21 are equalized to the equal voltage VA1, as shown in FIG. 41. Consequently, the difference voltage xcex94VO between the nodes NO1 and NO2 is expressed by the following equation, as described using FIG. 41:
xcex94VO=VO(+)xe2x88x92VO(xe2x88x92)=(xcex94Vixe2x88x92xcex94VDA)K 
An output from the subtraction amplification circuit 111 in the preceding stage can be thus used as the set voltage VA1 inputted to the nodes N11 and N21. Accordingly, the voltage Vi (+) and the set voltage VA1 can be inputted to the node N11 without using a switch, and the voltage Vi (xe2x88x92) and the set voltage VA1 can be inputted to the node N21 without using a switch.
Furthermore, an arbitrary voltage can be used as the set voltage VA2 inputted to the node N30. For example, the high-potential side reference voltage VRT or the low-potential side reference voltage VRB can be also used as the set voltage VA2.
Furthermore, the set voltages VA1 and VA2 can be set in the vicinity of a power supply voltage or a ground voltage. Consequently, a low-voltage operation can be performed even if a CMOS switch is employed.
As a result, a high-accuracy analog-to-digital conversion circuit that causes switch noise to be reduced and can perform a low-voltage operation is realized.
In recent years, the further increase in the conversion speed has been also demanded for the analog-to-digital conversion circuit with the increase in speed of electronic equipment. Therefore, an analog-to-digital conversion circuit whose conversion speed is further increased is proposed in JP-A-11-88172.
FIG. 43 is a block diagram showing a conventional analog-to-digital conversion circuit disclosed in JP-A-11-88172. The analog-to-digital conversion circuit 102 shown in FIG. 43 has a 10-bit four-stage pipeline structure.
In FIG. 43, the analog-to-digital conversion circuit 102 comprises a sample-and-hold circuit 2, a first-stage circuit 3, a second-stage circuit 4, a third-stage circuit 5, a fourth-stage circuit 6, a plurality of latch circuits 7, and an output circuit 8.
Each of the first (initial)- to third-stage circuits 3 to 5 comprises a sub-A/D converter 9, a D/A converter 10, an operational amplification circuit 11, a subtraction circuit 12, an operational amplification circuit 13, and a subtraction amplification circuit 14. The subtraction circuit 12 and the operational amplifier circuit 13 constitute a subtraction amplification circuit 14. The gain of each of the operational amplification circuits 11 and 13 in each of the circuits 3 to 5 is two. The fourth (final)-stage circuit 6 comprises only a sub-A/D converter 9.
In the analog-to-digital conversion circuit 102 shown in FIG. 43, the operational amplification circuits 11 and 13 in two stages are provided in each of the first- to third-stage circuits 3 to 5. Accordingly, the loop constant of each of the operational amplification circuits 11 and 13 can be reduced, and the load capacitance of each of the operational amplification circuits 11 and 13 is reduced. As a result, the conversion speed can be increased without improving the performance of each of the operational amplification circuits 11 and 13.
In the analog-to-digital conversion circuit 102 shown in FIG. 43, however, the analog input signal is amplified with the gain 2 by the operational amplification circuit 11 in each of the first- to third-stage circuits 3 to 5. When the input voltage range of the sub-A/D converter 9 and the output voltage range of the D/A converter 10 are set to the same value, therefore, the range of an output voltage supplied to one of input terminals of the subtraction amplification circuit 14 from the operation amplification circuit 11 and the range of an output voltage supplied to the other input terminal of the subtraction amplification circuit 14 from the D/A converter 10 differ from each other. In this case, the output voltage range of the operational amplification circuit 11 and the output voltage range of the D/A converter 10 must be corrected in any method such that they coincide with each other. Consequently, the structure of each of the circuits 3 to 5 in the analog-to-digital conversion circuit 102 becomes complicated, and the circuit scale thereof is increased.
The first-stage circuit 3 has a four-bit configuration, and each of the second- to fourth-stage circuits 4 to 6 has a 2-bit configuration. In each of the first- to third-stage circuits 3 to 5, the respective numbers of bits (bit configurations) of the sub-A/D converter 9 and the D/A converter 10 are set to the same value.
In the above-mentioned analog-to-digital conversion circuit 102, when the voltage range of an analog input signal Vin is set to VINp-p, the full-scale range of the sub-A/D converter 9 in the first-stage circuit 3 is equal to the voltage range VINp-p of the analog input signal Vin. The full-scale ranges of the sub-A/D converters 9 in the second- to fourth-stage circuits 4 to 6 are respectively equal to the output voltage ranges VINp-p/8 of the subtraction amplification circuits 14 in the first- to third-stage circuits 3 to 5.
The full-scale range of the D/A converter 10 in the first-stage circuit 3 is equal to the voltage range VINp-p of the analog input signal Vin, similarly to that of the sub-A/D converter 9. The full-scale ranges of the D/A converters 10 in the second- and third-stage circuits 4 and 5 are VINp-p/4 which is twice the full-scale range of the sub-A/D converter 9 in order to be matched with the output voltage range of the operational amplification circuit 11 having the gain 2.
The operations of the analog-to-digital conversion circuit 102 shown in FIG. 43 will be then described. The sample-and-hold circuit 2 samples the analog input signal Vin, and holds the sampled analog input signal for a predetermined time period. The analog input signal Vin outputted from the sample-and-hold circuit 2 is transferred to the first-stage circuit 3.
In the first-stage circuit 3, the sub-A/D converter 9 subjects the analog input signal Vin at a voltage range VINp-p to A/D conversion. The full-scale range of the sub-A/D converter 9 is VINp-p, as described above. A digital output (29, 28, 27, 26), which is the result of the A/D conversion by the sub-A/D converter 9, is transferred to the D/A converter 10, and is also transferred to the output circuit 8 through the four latch circuits 7. The normal output voltage range of the D/A converter 10 is expressed by the following equation:
(resolution in first stage-1)xc3x97(full-scale range of D/A converter 10)/(resolution in first stage)=(24xe2x88x921)xc3x97(VINp-p)/24=15VINp-p/16 
On the other hand, the operational amplification circuit 11 samples, amplifies and holds the analog input signal Vin. The output voltage range of the operational amplification circuit 11 is expressed by the following equation:
(voltage range VINp-p of analog input signal Vin)xc3x97(gain of operational amplification circuit 11)=VINp-pxc3x971=VINp-p 
The subtraction amplification circuit 14 subtracts the analog input signal Vin outputted from the operational amplification circuit 11 and the result of the D/A conversion by the D/A converter 10, and amplifies the result of the subtraction. An output from the subtraction amplification circuit 14 is transferred to the second-stage circuit 4. The output voltage range of the subtraction amplification circuit 14 in the first stage is expressed by the following equation:
((output voltage range of operational amplification circuit 11)xe2x80x94(normal output voltage range of D/A converter 10))xc3x97(gain of subtraction amplification circuit 14)=((VINp-p)xe2x80x94(15VINp-p/16))xc3x972VINp-p/8 
In the second-stage circuit 4, the sub-A/D converter 9 subjects the output from the subtraction amplification circuit 14 to A/D conversion. The result of the A/D conversion by the sub-A/D converter 9 is transferred to the D/A converter 10, and is also transferred to the output circuit 8 through the three latch circuits 7. Consequently, an intermediate high order 2-bit digital output (25, 24) is obtained from the second-stage circuit 4. The normal output voltage range of the D/A converter 10 is expressed by the following equation:
(resolution in second stage-1)xc3x97(full-scale range of D/A converter 10)/(resolution in second stage)=(22xe2x88x921)xc3x97(VINp-p/4)/24=3VINp-p/16 
On the other hand, the operational amplification circuit 11 amplifies an output from the operational amplification circuit 13 in the first-stage circuit 3. The output voltage range of the operational amplification circuit 11 is expressed by the following equation:
(output voltage range of subtraction amplification circuit 14 in first stage)xc3x97(gain of operational amplification circuit 11)=(VINp-p/8)xc3x972=VINp-p/4 
The subtraction amplification circuit 14 subtracts the output from the operational amplification circuit 11 and the result of the D/A conversion by the D/A converter 10, and amplifies the result of the subtraction. An output from the subtraction amplification circuit 14 is transferred to the third-stage circuit 5. The output voltage range of the subtraction amplification circuit 14 in the second stage is expressed by the following equation:
((output voltage range of operational amplification circuit 11)xe2x88x92(normal output voltage range of D/A converter 10)xc3x97(gain of subtraction amplification circuit 14)=((VINp-p/4)xe2x88x92(3VINp-p/16))xc3x972=VINp-p/8 
The third-stage circuit 5 performs the same operations as those of the second-stage circuit 4 with respect to the output from the subtraction amplification circuit 14 in the second-stage circuit 4. Consequently, an intermediate low order 2-bit digital output (23, 22) is obtained from the third-stage circuit 5. The output voltage range of each of the circuits is the same as that in the second-stage circuit 4.
In the fourth-stage circuit 6, the sub-A/D converter 9 subjects the output from the subtraction amplification circuit 14 in the third-stage circuit 5 to A/D conversion, thereby obtaining a low order 2-bit digital output (21, 20).
The digital outputs from the first- to fourth-stage circuits 3 to 6 simultaneously reach the output circuit 8 through the respective latch circuits 7. That is, the latch circuits 7 are provided to synchronize the respective digital outputs from the circuits 3 to 6 with each other.
The output circuit 8 outputs a 10-bit digital output Dout of the analog input signal Vin in parallel after digital correction processing, when required.
Even if the number of converted bits thus increases to reduce the LSB (Least Significant Bit) with the decrease in the power supply voltage, the resolution of the sub-A/D converter 9 can be improved, thereby obtaining sufficient conversion accuracy.
FIG. 44(a) is a circuit diagram showing the structure of the subtraction amplification circuit in the analog-to-digital conversion circuit shown in FIG. 23, and FIG. 44(b) is a diagram for explaining the operations of the subtraction amplification circuit shown in FIG. 44(a).
In FIG. 44, an inverse input terminal of an operational amplifier 101 is connected to a node nb, and a non-inverse input terminal thereof is grounded. Further, an output terminal of the operational amplifier 101 is connected to a node no, and is connected to the inverse input terminal through a capacitor 102. A switch SW1 is connected between the inverse input terminal and the non-inverse input terminal of the operational amplifier 101, and a capacitor 103 is connected between the node nb and a node na. The node na is connected to a node n1 through a switch SW2, and is connected to a node n2 through a switch SW3. Each of the switches SW2 and SW3 is generally a CMOS switch composed of a CMOS (Complementary Metal-Oxide Semiconductor) field effect transistor.
A voltage V1 is inputted to the node n1, and a voltage V2 is inputted to the node n2, and a voltage Vo is outputted from the node no.
While referring to FIG. 44(b), the operations of the subtraction amplification circuit shown in FIG. 44(a) will be described. Let C be the capacitance value of the capacitor 101, KC be the capacitance value of the capacitor 103, and VG be a ground potential. K is a constant.
First, the switch SW1 and the switch SW2 are turned on, and the switch SW3 is turned off. Consequently, a voltage at the node na is V1. Further, a voltage at the node no is zero. At this time, charges Qa at the node nb are expressed by the following equation:
Qa=(VGxe2x88x92V1)KC 
After the switch SW1 is then turned off, the switch SW2 is turned off, and the switch SW3 is turned on. Consequently, the voltage at the node na is V2. Further, the voltage at the node no is VO. At this time, the node nb is virtually grounded. Accordingly, charges Qb at the node nb are expressed by the following equation:
Qb=(VGxe2x88x92V2)KC+(VGxe2x88x92VO)C 
There is no path through which charge flows out at the node nb. Accordingly, Qa=Qb from the principle of conservation of charge. Consequently, the following equation holds:
(VGxe2x88x92V1)KC=(VGxe2x88x92V2)KC+(VGxe2x88x92VO)C 
From the foregoing equation, the voltage VO at the node no is expressed by the following equation:
VO=VG+(V1xe2x88x92V2)K 
In such a way, the voltage V2 is subtracted from the voltage V1, and the result of the subtraction is amplified by a factor of K.
Consequently, the subtraction amplification circuit has the function of outputting the difference between the voltage V1 and the voltage V2 with a gain determined by the ratio of the capacitance of the capacitor 103 to the capacitance of the capacitor 102. For example, KC=C(K=1) is set, thereby causing the subtraction amplification circuit to have a sample-and-hold function with a gain of one.
FIG. 45 is a diagram showing the structure of a sub-A/D converter used in the analog-to-digital conversion circuit shown in FIG. 43.
In a parallel-type analog-to-digital converter 9 shown in FIG. 45, a plurality of comparators 900 are arranged. The analog input voltage Vin is supplied to respective one input terminals of the plurality of comparators 900, and reference voltages obtained by dividing a voltage between a high-potential side reference voltage VRT and a low-potential side reference voltage VRB by a plurality of resistors R are respectively supplied to the other input terminals thereof. Each of the comparators 900 compares the voltage at the one input terminal with the voltage at the other input terminal. The result of the comparison by each of the plurality of comparators 900 is encoded by an encoder 910, thereby making it possible to obtain a digital code Dcode.
When the voltage range of the analog input signal fed to the analog-to-digital conversion circuit is changed, or the system of the analog input signal fed to the analog-to-digital conversion circuit is changed between a differential double-ended input and a single ended input, the specification of the analog-to-digital conversion circuit must be changed.
The differential double-ended input and the single-ended input will be herein described. FIGS. 46(a) and 46(b) are diagrams for explaining A/D conversion in the differential double-ended input and the single-ended input. A horizontal axis represents the analog input voltage Vin, and a vertical axis represents the outputted digital code Dcode.
As shown in FIG. 46(a), at the time of the differential double-ended input, a positive side analog input voltage Vin (+) and a negative side analog input voltage Vin (xe2x88x92) of the analog input signal Vin complementarily change. Consequently, the difference between the positive side analog input voltage Vin (+) and the negative side analog input voltage Vin (xe2x88x92) is a voltage range VINp-p of the analog input signal Vin.
When the positive side analog input voltage Vin (+) changes in a range from 1.0 V to 2.0 V, and the negative side analog input voltage Vin (xe2x88x92) changes in a range from 2.0 V to 1.0 V, as shown in FIG. 46(a), therefore, the voltage range of the analog input signal Vin is 2.0 V from an operation of Vin (+)xe2x88x92Vin (xe2x88x92).
On the other hand, as shown in FIG. 46(b), at the time of the single-ended input, only the positive side analog input voltage Vin (+) changes, as shown in FIG. 46(b). Consequently, the voltage range of the positive side analog input voltage Vin (+) is the voltage range of the analog input signal Vin.
When the positive side analog input voltage Vin (+) changes in a range from 1.0 V to 2.0 V, as shown in FIG. 46(b), therefore, the voltage range of the analog input signal is 1.0 V.
That is, when the voltage range of the analog input signal Vin of the differential double-ended input system is taken as 2VINp-p, the voltage range of the analog input signal Vin of the single-ended input system is VINp-p.
In the differential double-ended input system and the single-ended input system, the voltage ranges of the analog input signals thus differ even if the ranges of the changes in the analog input voltages are the same.
In the above-mentioned conventional analog-to-digital conversion circuit, when the voltage range of the analog input signal is changed, or the input system of the analog input signal is changed, the circuit structure must be redesigned.
An object of the present invention is to provide an analog-to-digital conversion circuit whose conversion speed is increased while keeping high conversion accuracy without complicating the circuit structure and increasing the circuit scale.
Another object of the present invention is to provide a pipeline-type analog-to-digital conversion circuit capable of easily changing the voltage range of an analog input signal or changing an input system between a differential double-ended input and a single-ended input without redesigning the circuit structure.
An analog-to-digital conversion circuit according to an aspect of the present invention has a multi-stage pipeline structure comprising a plurality of stages of circuits, each of the stages of circuits excluding the final-stage circuit comprising an analog-to-digital converter that converts an inputted analog signal into a digital signal, a first operational amplification circuit that amplifies the inputted analog signal, a digital-to-analog converter that converts the digital signal outputted from the analog-to-digital converter into an analog signal, and a second operational amplification circuit that amplifies the difference between the analog signal outputted from the first operational amplification circuit and the analog signal outputted from the digital-to-analog converter. In at least one of the stages of circuits excluding the final-stage circuit, the first operational amplification circuit has a gain larger than one, and the voltage range of the digital-to-analog converter and the voltage range of the analog-to-digital conversion circuit are independently set, respectively, such that the voltage range of the first operational amplification circuit and the voltage range of the digital-to-analog converter are equal to each other.
In the analog-to-digital conversion circuit according to the present invention, even when the operational amplification circuit has the gain larger than one by independently setting the voltage range of the digital-to-analog converter and the voltage range of the analog-to-digital conversion circuit, respectively, the output voltage range of the first operational amplification circuit and the voltage range of the digital-to-analog converter can be made equal to each other. Consequently, the degree of freedom of the design of each of the stages of circuits is increased. Therefore, it is possible to respectively design the analog-to-digital converter, the digital-to-analog converter, the first operational amplification circuit, and the second operational amplification circuit which are constituent elements of each of the stages of circuits at suitable voltage ranges by considering the power consumption and the area occupied by the circuit.
Furthermore, each of the stages of circuits excluding the final-stage circuit comprises the first operational amplification circuit and the second operational amplification circuit. Accordingly, the loop constants of the first operational amplification circuit and the second operational amplification circuit can be reduced, and the load capacitances of the first operational amplification circuit and the second operational amplification circuit are reduced. Consequently, the limit operating frequency of each of the first operational amplification circuit and the second operational amplification circuit is increased. Therefore, it is possible to increase the speed of the conversion operation while keeping high conversion accuracy without improving the performance of each of the first operational amplification circuit and the second operational amplification circuit itself.
As a result, the analog-to-digital conversion circuit whose conversion operation is increased in speed while keeping high conversion accuracy without complicating the circuit structure and increasing the circuit scale.
In at least one of the stages of circuits, the ratio of the voltage range of the digital-to-analog converter to the voltage range of the analog-to-digital conversion circuit may be equal to the gain of the first operational amplification circuit.
In this case, the ratio of the voltage range of the digital-to-analog converter to the voltage range of the analog-to-digital conversion circuit is equal to the gain of the first operational amplification circuit, thereby making it possible to make the voltage range of the first operational amplification circuit and the voltage range of the digital-to-analog converter equal to each other. Consequently, the second operational amplification circuit can amplify the difference between the analog signals at the equal voltage ranges.
In at least one of the stages of circuits, the analog-to-digital converter may operate on the basis of a reference voltage having a first voltage range, the digital-to-analog converter may operate on the basis of a reference voltage having a second voltage range, and the first voltage range and the second voltage range may be independently set, respectively, such that the voltage range of the first operational amplification circuit and the output voltage range of the digital-to-analog converter are equal to each other.
In this case, the analog-to-digital converter operates on the basis of the reference voltage having the first voltage range, the digital-to-analog converter operates on the basis of the reference voltage having the second voltage range, and the first voltage range and the second voltage range are independently set, respectively, thereby making it possible to make the output voltage range of the first operational amplification circuit and the voltage range of the digital-to-analog converter equal to each other.
In at least one of the stages of circuits, the ratio of the second voltage range to the first voltage range may be equal to the gain of the first operational amplification circuit.
In this case, the ratio of the second voltage range to the first voltage range is equal to the gain of the first operational amplification circuit, so that the output voltage range of the first operational amplification circuit and the voltage range of the digital-to-analog converter are equal to each other.
An analog-to-digital conversion circuit according to another aspect of the present invention has a multi-stage pipeline structure comprising a plurality of stages of circuits, each of the stages of circuits excluding the final-stage circuit comprising an analog-to-digital converter that converts an inputted analog signal into a digital signal, a first operational amplification circuit that amplifies the inputted analog signal, a digital-to-analog converter that converts the digital signal outputted from the analog-to-digital converter into an analog signal, and a second operational amplification circuit that amplifies the difference between the analog signal outputted from the first operational amplification circuit and the analog signal outputted from the digital-to-analog converter. In at least one of the stages of circuits excluding the final-stage circuit, the first operational amplification circuit has a gain larger than one, the digital-to-analog converter has a capacitance array to which a plurality of capacitances for generating a voltage of the analog signal corresponding to the digital signal are connected in an array shape, the second operational amplification circuit has an input capacitance, a feedback capacitance, and an operational amplifier, amplifies the analog signal outputted from the first operational amplification circuit with a first gain determined by the value of the input capacitance and the value of the feedback capacitance, amplifies the analog signal generated in the capacitance array by the digital-to-analog converter with a second gain determined by the value of the capacitance array and the value of the feedback capacitance, and outputs the difference between the analog signal amplified with the first gain and the analog signal amplified with the second gain, and the value of the capacitance array and the value of the input capacitance are independently set, respectively, such that the output voltage range of the first operational amplification circuit multiplied by the first gain and the voltage range of the digital-to-analog converter multiplied by the second gain are equal to each other.
In this case, the analog signal outputted from the first operational amplification circuit is amplified with the first gain, and the analog signal outputted from the digital-to-analog converter is amplified with the second gain, so that the difference between the amplified analog signals is outputted. The value of the capacitance array and the value of the input capacitance are independently set, respectively, thereby making it possible to make the output voltage range of the first operational amplification circuit multiplied by the first gain and the voltage range of the digital-to-analog converter multiplied by the second gain equal to each other.
In at least one of the stages of circuits, the ratio of the value of the capacitance array to the value of the input capacitance may be equal to the gain of the first operational amplification circuit.
In this case, the ratio of the value of the capacitance array to the value of the input capacitance is equal to the gain of the first operational amplification circuit, so that the output voltage range of the first operational amplification circuit multiplied by the first gain and the voltage range of the digital-to-analog converter multiplied by the second gain are equal to each other.
In at least one of the stages of circuits, the operational amplifier in the second operational amplification circuit may have one input terminal to which the capacitance array is connected and has the other input terminal and an output terminal, the feedback capacitance in the second operational amplification circuit may be connected between the one input terminal and the output terminal of the operational amplifier, and the input capacitance in the second operational amplification circuit may be connected in parallel with the capacitance array to the one input terminal of the operational amplifier, and second operational amplification circuit may further comprise a switch circuit that brings about a short-circuited state between the one input terminal and the other input terminal of the operational amplifier, and feeds the analog signal outputted from the operational amplifier to an input end of the input capacitance and feeds an arbitrary first set voltage to an input end of the capacitance array, then brings about an opened state between the one input terminal and the other input terminal of the operational amplifier, and feeds an arbitrary second set voltage to the input end of the input capacitance and feeds the analog signal outputted from the digital-to-analog converter to the input end of the capacitance array.
In this case, the analog signal outputted from the first operational amplification circuit is amplified with the first gain, and the analog signal outputted from the digital-to-analog converter is amplified with the second gain. The amplified analog signals are subtracted using the set voltage as a medium without switching the analog signals using a switch, thereby outputting the result of the subtraction. Consequently, noise is reduced, and a low-voltage operation can be performed.
In at least one of the stages of circuits, the set voltage of the second operational amplification circuit may be a predetermined voltage of the analog signal outputted from the first operational amplification circuit.
In this case, no switch or circuit that feeds the set voltage is required, thereby further reducing noise as well as simplifying the circuit structure.
In at least one of the stages of circuits, the first operational amplification circuit may output first and second differential analog signals, the capacitance array of the digital-to-analog converter may comprise first and second capacitance arrays for respectively generating voltages of third and fourth differential analog signals corresponding to the digital signal, the operational amplifier in the second operational amplification circuit may have one input terminal to which the first capacitance array is connected, the other input terminal to which the second capacitance array is connected, one output terminal, and the other output terminal, the feedback capacitance may comprise a first feedback capacitance connected between the one input terminal and the one output terminal of the operational amplifier, and a second feedback capacitance connected between the other input terminal and the other output terminal of the operational amplifier, the input capacitance may comprise a first input capacitance connected in parallel with the first capacitance array to the one input terminal of the operational amplifier and a second input capacitance connected in parallel with the second capacitance array to the other input terminal of the operational amplifier, the differential amplifier may further comprise a switch circuit that connects the one and other input terminals of the operational amplifier to a predetermined reference potential, and respectively feeds the first and second differential analog signals outputted from the first operational amplification circuit to input ends of the first and second input capacitances and respectively feeds an arbitrary first set voltage to input ends of the first and second capacitance arrays, then disconnects the one and other input terminals of the operational amplifier from the reference potential, and respectively feeds an arbitrary second set voltage to the input ends of the first and second input capacitances and respectively feeds third and fourth differential analog signals outputted from the digital-to-analog converter to the input ends of the first and second capacitance arrays, and the value of the first capacitance array and the value of the first input capacitance may be independently set, respectively, such that the output voltage range of the first operational amplification circuit multiplied by the first gain and the voltage range of the digital-to-analog converter multiplied by the second gain are equal to each other.
In this case, the value of the first capacitance array and the value of the first input capacitance are independently set, respectively, and the value of the second capacitance array and the value of the second input capacitance are independently set, respectively, thereby making it possible to make the output voltage range multiplied by the first gain, of the first operational amplification circuit that outputs the differential analog signal and the voltage range multiplied by the second gain, of the digital-to-analog converter that outputs the differential analog signal equal to each other.
In at least one of the stages of circuits, the ratio of the value of the first capacitance array to the value of the first input capacitance may be equal to the gain of the first operational amplification circuit, and the ratio of the second capacitance array to the value of the second input capacitance may be equal to the gain of the first operational amplification circuit.
In this case, the ratio of the value of the first capacitance array to the value of the first input capacitance and the ratio of the value of the second capacitance array to the value of the second input capacitance are equal to the gain of the first operational amplification circuit, thereby making the output voltage range multiplied by the first gain, of the first operational amplification circuit that outputs the differential analog signal and the voltage range multiplied by the second gain, of the digital-to-analog converter that outputs the differential analog signal equal to each other.
In at least one of the stages of circuits, the second set voltage of the second operational amplification circuit may be an output voltage equalized in the first operational amplification circuit.
In this case, no switch or circuit that feeds the second set voltage is required, thereby further reducing noise as well as simplifying the circuit structure.
An analog-to-digital conversion circuit according to still another aspect of the present invention has a multi-stage pipeline structure comprising a plurality of stages of circuits, each of the stages of circuits excluding the final-stage circuit comprising an analog-to-digital converter that converts an inputted analog signal into a digital signal, a first operational amplification circuit that amplifies the inputted analog signal, a digital-to-analog converter that converts the digital signal outputted from the analog-to-digital converter into an analog signal, and a second operational amplification circuit that amplifies the difference between the analog signal outputted from the first operational amplification circuit and the analog signal outputted from the digital-to-analog converter. In at least one of the stages of circuits excluding the final-stage circuit, the operational amplification circuit has a gain larger than one, the analog-to-digital converter operates on the basis of a reference voltage having a first voltage range, and the digital-to-analog converter operates on the basis of a reference voltage having a second voltage range, the digital-to-analog converter has a capacitance array to which a plurality of capacitances for generating a voltage of the analog signal corresponding to the digital signal are connected in an array shape, the second operational amplification circuit has an input capacitance, a feedback capacitance, and a first operational amplifier, amplifies the analog signal outputted from the operational amplification circuit with a first gain determined by the value of the input capacitance and the value of the feedback capacitance, amplifies the analog signal generated in the capacitance array by the digital-to-analog converter with a second gain determined by the value of the capacitance array and the value of the feedback capacitance, and outputs the difference between the analog signal amplified with the first gain and the analog signal amplified with the second gain, and the first voltage range and the second voltage range are independently set, respectively, and the value of the capacitance array and the value of the input capacitance are independently set, respectively, such that the output voltage range of the first operational amplification circuit multiplied by the first gain and the voltage range of the digital-to-analog converter multiplied by the second gain are equal to each other.
In this case, the analog-to-digital converter operates on the basis of the reference voltage having the first voltage range, the digital-to-analog converter operates on the basis of the reference voltage having the second voltage range, the first voltage range and the second voltage range are independently set, respectively, and the value of the capacitance array and the value of the input capacitance are independently set, respectively, thereby making it possible to make the output voltage range of the first operational amplification circuit multiplied by the first gain and the voltage range of the digital-to-analog converter multiplied by the second gain equal to each other.
An analog-to-digital conversion circuit according to still another aspect of the present invention has a multi-stage pipeline structure comprising a plurality of stages of circuits, each of the stages of circuits excluding the final-stage circuit comprising an analog-to-digital converter that converts an inputted analog signal into a digital signal, a digital-to-analog converter that converts the digital signal outputted from the analog-to-digital converter into an analog signal, and a first operational amplification circuit that amplifies the difference between the inputted analog signal and the analog signal outputted from the digital-to-analog converter, the final-stage circuit comprising an analog-to-digital converter that converts the inputted analog signal into a digital signal, at least one of the stages of circuits excluding the final-stage circuit comprising at least one of an analog-to-digital converter having switching means for switching a voltage range among a plurality of ranks, a digital-to-analog converter having switching means for switching a voltage range among a plurality of ranks, and a first operational amplification circuit having switching means for switching a gain among a plurality of values, and/or the final-stage circuit comprising an analog-to-digital converter having switching means for switching a voltage range among a plurality of ranks.
In the analog-to-digital conversion circuit according to the present invention, at least one of the stages of circuits excluding the final-stage circuit comprises at least one of the analog-to-digital converter having the switching means for switching the voltage range among the plurality of ranks, the digital-to-analog converter having the switching means for switching the voltage range among the plurality of ranks, and the first operational amplification circuit having the switching means for switching the gain among the plurality of values, and/or the final-stage circuit comprises the analog-to-digital converter having the switching means for switching the voltage range among the plurality of ranks, thereby making it possible to switch at least one of the voltage range of the analog-to-digital conversion circuit, the voltage range of the digital-to-analog converter, and the gain of the first operational amplification circuit.
Even if the voltage range of the analog input signal is changed by changing the differential double-ended input system to the single-ended input system, therefore, the circuit structure need not be redesigned. Further, even when the voltage range of the analog input signal of the single-ended input system is changed, or the voltage range of the analog input signal of the differential double-ended input system is changed, the circuit structure need not be redesigned.
Consequently, it is possible to easily change the voltage range of the analog input signal or change the input system between the differential double-ended input and the single-ended input without redesigning the circuit structure.
As a result, it is possible to shorten a period during which the analog-to-digital conversion circuit is developed as well as easily reduce the power consumption by optimizing the voltage range.
Each of the stages of circuits excluding the final-stage circuit may further comprise a second operational amplification circuit that amplifies the inputted analog signal and feeds the amplified analog signal to the first operational amplification circuit, and the second operational amplification circuit in at least one of the stages of circuits excluding the final-stage circuit may have switching means for switching a gain among a plurality of values.
In this case, the gain of the second operational amplification circuit in at least one of the stages of circuits is switched among the plurality of values, thereby making it possible to easily change the voltage range of the analog input signal or easily change the input system between the differential double-ended input and the single-ended input without redesigning the circuit structure.
The first operational amplification circuit in at least one of the stages of circuits excluding the final-stage circuit may have switching means for switching a gain among a plurality of values.
In this case, the gain of the first operational amplification circuit in at least one of the stages of circuits is switched among the plurality of values, thereby making it possible to easily change the voltage range of the analog input signal or change the input system between the differential double-ended input and the single-ended input without redesigning the circuit structure.
The analog-to-digital converter in at least one of the stages of circuits may have switching means for switching a voltage range among a plurality of ranks.
In this case, the voltage range of the analog-to-digital converter in at least one of the stages of circuits can be switched among the plurality of ranks, thereby making it possible to easily change the voltage range of the analog input signal or change the input system between the differential double-ended input and the single-ended input without redesigning the circuit structure.
The digital-to-analog converter in at least one of the stages of circuits excluding the final-stage circuit may have switching means for switching a voltage range among a plurality of ranks.
In this case, the voltage range of the digital-to-analog converter in at least one of the stages of circuits is switched among the plurality of ranks, thereby making it possible to easily change the voltage range of the analog input signal or change the input system between the differential double-ended input and the single-ended input without redesigning the circuit structure.
The second operational amplification circuit in at least one of the stages of circuits may have an input capacitance, a feedback capacitance, and an operational amplifier, and amplify the inputted analog signal with a gain determined by the value of the input capacitance and the value of the feedback capacitance, and the switching means may comprise a variable part that variably sets at least one of the value of the input capacitance and the value of the feedback capacitance.
In this case, the inputted analog signal is amplified with the gain determined by the value of the input capacitance and the value of the feedback capacitance. Consequently, at least one of the value of the input capacitance of the operational amplifier and the value of the feedback capacitance is changed, thereby making it possible to easily switch the gain of the second operational amplification circuit.
The variable part may comprise a switching part that switches part of the input capacitance or the feedback capacitance to a separated state or a short-circuited state.
In this case, part of the input capacitance or the feedback capacitance is switched to the separated state or the short-circuited state by the switching part, thereby making it possible to change the input capacitance or the feedback capacitance of the operational amplifier. Consequently, it is possible to easily switch the gain of the second operational amplification circuit.
The first operational amplification circuit in at least one of the stages of circuits may have an input capacitance, a feedback capacitance, and an operational amplifier, and amplify the inputted analog signal with a gain determined by the value of the input capacitance and the value of the feedback capacitance, and the switching means may comprise a variable part that variably sets at least one of the value of the input capacitance and the value of the feedback capacitance.
In this case, the inputted analog signal is amplified with the gain determined by the value of the input capacitance and the value of the feedback capacitance. Consequently, at least one of the value of the input capacitance of the operational amplifier and the value of the feedback capacitance thereof is changed, thereby making it possible to easily switch the gain of the first operational amplification circuit.
The variable part may comprise a switching part that switches part of the input capacitance or the feedback capacitance to a separated state or a short-circuited state.
In this case, part of the input capacitance or the feedback capacitance is switched to the separated state or the short-circuited state by the switching part, thereby making it possible to change the input capacitance or the feedback capacitance of the operational amplifier. Consequently, it is possible to easily switch the gain of the first operational amplification circuit.
The feedback capacitance may comprise first and second capacitances provided in parallel or in series between the input terminal and the output terminal of the operational amplifier, and the switching part may be connected in series or in parallel with the second capacitance.
When the switching part is brought into the connected state, the first and second capacitances are connected in parallel or in series between the input terminal and the output terminal of the operational amplifier. Consequently, the feedback capacitance increases or decreases. Further, when the switching part is brought into the disconnected state, only the first capacitance is connected between the input terminal and the output terminal of the operational amplifier. Consequently, the feedback capacitance decreases or increases.
The switching part may be connected to the output terminal of the operational amplifier.
In a case where the second capacitance is connected to the output side of the switching part, even if the switching part is set to the disconnected state, the parasitic capacitance of the second capacitance is charged. Consequently, the parasitic capacitance must be considered at the time of setting the gain, so that the gain varies depending on the variation in the parasitic capacitance. When the switching part is set to the disconnected state by being connected to the output side of the second capacitance, the second capacitance, together with the parasitic capacitance, is separated from the output terminal by the switching part. Consequently, the parasitic capacitance of the second capacitance need not be considered when the gain is set, so that the gain does not vary depending on the variation in the parasitic capacitance.
The input capacitance may be provided in parallel or in series with the input terminal of the operational amplifier.
When the switching part is brought into the connected state, the first and second capacitances are connected in parallel or in series with the input terminal of the operational amplifier. Consequently, the input capacitance increases or decreases. On the other hand, when the switching part is brought into the disconnected state, only the first capacitance is connected to the input terminal of the operational amplifier. Consequently, the input capacitance decreases or increases.
The switching part may be connected to the input side of the second capacitance.
In a case where the second capacitance is connected to the input side of the switching part, when the switching part is set to the disconnected state, the parasitic capacitance of the second capacitance is charged. When the gain is set, therefore, the parasitic capacitance must be considered, so that the gain varies depending on the variation in the parasitic capacitance. When the switching part is set to the disconnected state by being connected to the input side of the second capacitance, the second capacitance, together with the parasitic capacitance, is separated from the node receiving the input signal by the switching part. Consequently, the parasitic capacitance of the second capacitance need not be considered when the gain is set, so that the gain does not vary depending on the variation in the parasitic capacitance.
The analog-to-digital converter in at least one of the stages of circuits may comprise a reference voltage generation circuit that generates a plurality of reference voltages, and a plurality of comparators that compare the plurality of reference voltages generated by the reference voltage generation circuit with the inputted analog signal, and the switching means may comprise a variable part that variably sets the plurality of reference voltages generated by the reference voltage generation circuit.
In this case, the reference voltage generated by the reference voltage generation circuit is changed, thereby making it possible to change the voltage range of the reference voltage. Consequently, it is possible to easily switch the voltage range of the analog-to-digital converter.
The digital-to-analog converter in at least one of the stages of circuits excluding the final-stage circuit may comprise a reference voltage generation circuit that generates a reference voltage, a plurality of capacitances connected to a common terminal, and a plurality of switches, connected between the reference voltage generation circuit and the plurality of capacitances, which respectively feed the reference voltage generated by the reference voltage generation circuit to the plurality of capacitances in response to an inputted digital signal, and the switching means may comprise a variable part that variably sets the reference voltage generated by the reference voltage generation circuit.
In this case, the reference voltage generated by the reference voltage generation circuit is changed, thereby making it possible to change the voltage range of the reference voltage. Consequently, it is possible to easily switch the voltage range of the digital-to-analog converter.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.